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ltc2452 1 2452fc typical application features applications description ultra-tiny, differential, 16-bit ? adc with spi interface the ltc ? 2452 is an ultra-tiny, fully differential, 16-bit, analog-to-digital converter. the ltc2452 uses a single 2.7v to 5.5v supply and communicates through an spi interface. the adc is available in an 8-pin, 3mm 2mm dfn package or tsot-23 package. it includes an integrated oscillator that does not require any external components. it uses a delta-sigma modulator as a converter core and has no latency for multiplexed applications. the ltc2452 includes a proprietary input sampling scheme that reduces the average input sampling current several orders of magnitude when compared to conventional delta-sigma converters. additionally, due to its architecture, there is negligible current leakage between the input pins. the ltc2452 can sample at 60 conversions per second, and due to the very large oversampling ratio, has extremely relaxed antialiasing requirements. the ltc2452 includes continuous internal offset and full-scale calibration algo - rithms which are transparent to the user, ensuring accuracy over time and over the operating temperature range. the converter has an external ref pin and the differential input voltage range can extend up to v ref . following a single conversion, the ltc2452 can automati - cally enter a sleep mode and reduce its supply current to less than 0.2a. if the user reads the adc once a second, the ltc2452 consumes an average of less than 50w from a 2.7v supply. integral nonlinearity, v cc = 3v n v cc differential input range n 16-bit resolution (including sign), no missing codes n 2lsb offset error n 4lsb full-scale error n 60 conversions per second n single conversion settling time for multiplexed applications n single-cycle operation with auto shutdown n 800a supply current n 0.2a sleep current n internal oscillatorno external components required n spi interface n ultra-tiny 3mm 2mm dfn and tsot-23 packages n system monitoring n environmental monitoring n direct temperature measurements n instrumentation n industrial process control n data acquisition n embedded adc upgrades l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and no latency is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 6208279, 6411242, 7088280, 7164378. differential input voltage (v) ?3 inl (lsb) 1 3 2452 ta01b ?1 0 2 ?2 ?3 ?1?2 1 2 0 3 t a = ?45c, 25c, 90c 10k 10k 10k r cs 3-wire spi interface sck sdo 0.1f 0.1f 10f 2.7v to 5.5v 0.1f in + ref v cc gnd in ? ltc2452 2452 ta01a
ltc2452 2 2452fc pin configuration absolute maximum ratings supply voltage (v cc ) ................................... C0.3v to 6v analog input voltage (v in + , v in C ) .. C0.3v to (v cc + 0.3v) reference voltage (v ref ) .............. C0.3v to (v cc + 0.3v) digital voltage (v sdo , v sck , v cs ) .. C0.3v to (v cc + 0.3v) (notes 1, 2) top view 9 dd8 package 8-lead (3mm 2mm) plastic dfn 5 6 7 8 4 3 2 1sck gnd ref v cc sdo cs in + in ? c/i grade t jmax = 125c, ja = 76c/w exposed pad (pin 9) is gnd, must be soldered to pcb sck 1 gnd 2 ref 3 v cc 4 8 sdo 7 cs 6 in + 5 in ? top view ts8 package 8-lead plastic tsot-23 c/i grade t jmax = 125c, ja = 140c/w order information electrical characteristics parameter conditions min typ max units resolution (no missing codes) (note 3) l 16 bits integral nonlinearity (note 4) l 1 10 lsb offset error l 2 10 lsb offset error drift 0.02 lsb/c gain error l 0.01 0.02 % of fs gain error drift 0.02 lsb/c transition noise 2.2 v rms power supply rejection dc 80 db the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 2) lead free finish tape and reel (mini) tape and reel part marking* package description temperature range ltc2452cddb#trmpbf ltc2452cddb#trpbf ldnj 8-lead plastic (3mm 2mm) dfn 0c to 70c ltc2452iddb#trmpbf ltc2452iddb#trpbf ldnj 8-lead plastic (3mm 2mm) dfn C40c to 85c ltc2452cts8#trmpbf ltc2452cts8#trpbf ltdpk 8-lead plastic tsot-23 0c to 70c ltc2452its8#trmpbf ltc2452its8#trpbf ltdpk 8-lead plastic tsot-23 C40c to 85c trm = 500 pieces. *temperature grades are identifed by a label on the shipping container. consult ltc marketing for parts specifed with wider operating temperature ranges. consult ltc marketing for information on lead based fnish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/ storage temperature range ................... C65c to 150c operating temperature range ltc2452c ................................................ 0c to 70c ltc2452i .............................................. C40c to 85c
ltc2452 3 2452fc analog inputs and references the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. symbol parameter conditions min typ max units v cc supply voltage l 2.7 5.5 v i cc supply current conversion sleep cs = gnd (note 6) cs = v cc (note 6) l l 800 0.2 1200 0.6 a a the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. symbol parameter conditions min typ max units v in + positive input voltage range l 0 v cc v v in C negative input voltage range l 0 v cc v v ref reference voltage range l 2.5 v cc v v or + + v ur + overrange + underrange voltage, in + v ref = 5v, v in C = 2.5v (see figure 3) 31 lsb v or C + v ur C overrange + underrange voltage, inC v ref = 5v, v in + = 2.5v (see figure 3) 31 lsb c in in + , in C sampling capacitance 0.35 pf i dc_leak(in + ) in + dc leakage current v in = gnd (note 10) v in = v cc (note 10) l l C10 C10 1 1 10 10 na na i dc_leak(in C ) in C dc leakage current v in = gnd (note 10) v in = v cc (note 10) l l C10 C10 1 1 10 10 na na i dc_leak(ref) ref dc leakage current v ref = 3v (note 10) l C10 1 10 na i conv input sampling current (note 5) 50 na the l denotes the specifcations which apply over the full operating temperature range,otherwise specifcations are at t a = 25c. (note 2) symbol parameter conditions min typ max units v ih high level input voltage l v cc C 0.3 v v il low level input voltage l 0.3 v i in digital input current l C10 10 a c in digital input capacitance 10 pf v oh high level output voltage i o = C800a l v cc C 0.5 v v ol low level output voltage i o = 1.6ma l 0.4 v i oz hi-z output leakage current l C10 10 a digital inputs and digital outputs power requirements
ltc2452 4 2452fc the l denotes the specifcations which apply over the full operating temperature range,otherwise specifcations are at t a = 25c. symbol parameter conditions min typ max units t conv conversion time l 13 16.6 23 ms f sck sck frequency range l 2 mhz t lsck sck low period l 250 ns t hsck sck high period l 250 ns t 1 cs falling edge to sdo low z (notes 7, 8) l 0 100 ns t 2 cs rising edge to sdo high z (notes 7, 8) l 0 100 ns t 3 cs falling edge to sck falling edge l 100 ns t kq sck falling edge to sdo valid (note 7) l 0 100 ns typical performance characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2. all voltage values are with respect to gnd. v cc = 2.7v to 5.5v unless otherwise specifed. v refcm = v ref /2, fs = v ref v in = v in + C v in C , Cv ref v in v ref ; v incm = (v in + + v in C )/2. note 3. guaranteed by design, not subject to test. note 4. integral nonlinearity is defned as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. guaranteed by design and test correlation. note 5: cs = v cc . a positive current is fowing into the dut pin. note 6: sck = v cc or gnd. sdo is high impedance. note 7: see figure 4. note 8: see figure 5. note 9: input sampling current is the average input current drawn from the input sampling network while the ltc2452 is actively sampling the input. note 10: a positive current is fowing into the dut pin. timing characteristics integral nonlinearity, v cc = 5v integral nonlinearity, v cc = 3v maximum inl vs temperature (t a = 25c, unless otherwise noted) differential input voltage (v) ?5 inl (lsb) 1 3 2452 g01 ?1 0 2 ?2 ?3 ?1?2?3?4 1 2 3 4 0 5 t a = ?45c, 25c t a = 90c differential input voltage (v) ?3 inl (lsb) 1 3 2452 g02 ?1 0 2 ?2 ?3 ?1?2 1 2 0 3 t a = ?45c, 25c, 90c temperature (c) ?50 inl (lsb) 1 3 2452 g03 ?1 0 2 ?2 ?3 ?25 25 50 75 0 100 v cc = v ref = 5v, 4.1v, 3v
ltc2452 5 2452fc typical performance characteristics offset error vs temperature gain error vs temperature transition noise vs temperature conversion mode power supply current vs temperature sleep mode power supply current vs temperature average power dissipation vs temperature, v cc = 3v power supply rejection vs frequency at v cc conversion time vs temperature (t a = 25c, unless otherwise noted) temperature (c) ?50 offset error (lsb) 1 5 2452 g04 ?1 0 2 3 4 ?2 ?3 ?4 ?5 ?25 25 50 75 0 100 v cc = v ref = 5v v cc = v ref = 4.1v v cc = v ref = 3v temperature (c) ?50 gain error (lsb) 1 5 2452 g05 ?1 0 2 3 4 ?2 ?3 ?4 ?5 ?25 25 50 75 0 100 v cc = v ref = 5v v cc = v ref = 4.1v v cc = v ref = 3v temperature (c) ?50 transition noise rms (v) 6 10 2452 g06 4 5 7 8 9 3 2 1 0 ?25 25 50 75 0 100 v cc = 5v v cc = 3v temperature (c) ?50 conversion current (a) 900 2452 g07 400 500 600 700 800 300 200 100 0 ?25 25 50 75 0 100 v cc = 5v v cc = 3v v cc = 4.1v temperature (c) ?50 sleep current (na) 250 2452 g08 150 200 100 50 0 ?25 25 50 75 0 100 v cc = 5v v cc = 3v v cc = 4.1v temperature (c) ?50 average power dissipation (w) 10000 2452 g09 1000 100 10 0 ?25 25 50 75 0 100 25hz output sample rate 10hz output sample rate 1hz output sample rate frequency at v cc (hz) 1 rejection (db) 0 2452 g10 ?20 ?40 ?60 ?80 ?100 ?120 10 1k 10k 100k 1m 100 10m temperature (c) ?50 conversion time (ms) 21 2452 g11 20 16 17 18 19 15 14 ?25 25 50 75 0 100 v cc = 5v, 4.1v, 3v
ltc2452 6 2452fc applications information block diagram pin functions sck (pin 1): serial clock input. sck synchronizes the serial data output. while digital data is available (the adc is not in convert state) and cs is low (adc is not in sleep state) a new data bit is produced at the sdo output pin following every falling edge applied to the sck pin. gnd (pin 2): ground. connect to a ground plane through a low impedance connection. ref (pin 3): reference input. the voltage on ref can have any value between 2.5v and v cc . the reference voltage sets the full-scale range. v cc (pin 4): positive supply voltage. bypass to gnd (pin 2) with a 10f capacitor in parallel with a low-se - ries-inductance 0.1f capacitor located as close to the ltc2452 as possible. in C (pin 5), in + (pin 6): differential analog input. cs (pin 7): chip select (active low) digital input. a low on this pin enables the sdo digital output. a high on this pin places the sdo output pin in a high imped- ance state. sdo (pin 8): three-state serial data output. sdo is used for serial data output during the data output state and can be used to monitor the conversion status. exposed pad (pin 9): ground. must be soldered to pcb ground. for prototyping purposes, this pad may remain foating. figure 1. functional block diagram 16-bit ? a/d converter decimating sinc filter sck ref v cc gnd in + in ? sdo cs 2452 bd ? 16-bit ? a/d converter spi interface internal oscillator 3 4 7 8 1 2, 9 6 5 converter operation converter operation cycle the ltc2452 is a low power, fully differential, delta-sigma analog-to-digital converter with a simple 3-wire spi in - terface (see figure 1). its operation is composed of three successive states: convert, sleep and data output. the operating cycle begins with the convert state, is followed by the sleep state, and ends with the data out - put state (see figure 2). the 3-wire interface consists of serial data output (sdo), serial clock input (sck), and the active low chip select input (cs). the convert state duration is determined by the ltc2452 conversion time (nominally 16.6 milliseconds). once
ltc2452 7 2452fc applications information figure 2. ltc2452 state transition diagram corresponds to the last completed conversion. a new bit of data appears at the sdo pin following each falling edge detected at the sck input pin and appears from msb to lsb. the user can reliably latch this data on every rising edge of the external serial clock signal driving the sck pin (see figure 3). the data output state concludes in one of two different ways. first, the data output state operation is completed once all 16 data bits have been shifted out and the clock then goes low. this corresponds to the 16 th falling edge of sck. second, the data output state can be aborted at any time by a low-to-high transition on the cs input. following either one of these two actions, the ltc2452 will enter the convert state and initiate a new conver - sion cycle. power-up sequence when the power supply voltage (v cc ) applied to the con - verter is below approximately 2.1v, the adc performs a power-on reset. this feature guarantees the integrity of the conversion result. when v cc rises above this critical threshold, the converter generates an internal power-on reset (por) signal for approximately 0.5ms. the por signal clears all internal registers. following the por signal, the ltc2452 starts a conversion cycle and follows the succession of states shown in figure 2. the frst conversion result following por is accurate within the specifcations of the device if the power supply voltage v cc is restored within the operating range (2.7v to 5.5v) before the end of the por time interval. ease of use the ltc2452 data output has no latency, flter settling delay or redundant results associated with the conversion cycle. there is a one-to-one correspondence between the conver - sion and the output data. therefore, multiplexing multiple analog input voltages requires no special actions. the ltc2452 performs offset calibrations every conver - sion. this calibration is transparent to the user and has no effect upon the cyclic operation described previously. the advantage of continuous calibration is stability of the adc performance with respect to time and temperature. data output sleep convert power-on reset yes 2452 f02 16th falling edge of sck or cs = high? sck = low and cs = low? no yes no started, this operation can not be aborted except by a low power supply condition (v cc < 2.1v) which generates an internal power-on reset signal. after the completion of a conversion, the ltc2452 enters the sleep state and remains there until both the chip select and serial clock inputs are low ( cs = sck = low). following this condition, the adc transitions into the data output state. while in the sleep state, whenever the chip select input is pulled high (cs = high), the ltc2452s power supply current is reduced to less than 200na. when the chip select input is pulled low (cs = low), and sck is maintained at a high logic level, the ltc2452 will return to a normal power consumption level. during the sleep state, the result of the last conversion is held indefnitely in a static register. upon entering the data output state, sdo outputs the sign (d15) of the conversion result. during this state, the adc shifts the conversion result serially through the sdo output pin under the control of the sck input pin. there is no latency in generating this data and the result
ltc2452 8 2452fc applications information the ltc2452 includes a proprietary input sampling scheme that reduces the average input current by several orders of magnitude when compared to traditional delta-sigma architectures. this allows external flter networks to in - terface directly to the ltc2452. since the average input sampling current is 50na, an external rc lowpass flter using 1k and 0.1f results in <1lsb additional error. additionally, there is negligible leakage current between in + and in C . reference voltage range the ltc2453 reference input range is 2.5v to v cc . for the simplest operation, ref can be shorted to v cc . input voltage range as mentioned in the output data format section, the output code is given as 32768?v in /v ref + 32768. for v in v ref , the output code is clamped at 65535 (all ones). for v in Cv ref , the output code is clamped at 0 (all zeroes). the ltc2452 includes a proprietary system that can, typically, digitize each input 8lsb above v ref and below gnd, if the differential input is within v ref . as an ex- ample (figure 3), if the user desires to measure a signal slightly below ground, the user could set v in C = gnd, and v ref = 5v. if v in + = gnd, the output code would be approximately 32768. if v in + = gnd C 8lsb = C1.22 mv, the output code would be approximately 32760. figure 3. output code vs v in + with v in C = 0 the total amount of overrange and underrange capability is typically 31lsb for a given device. the 31lsb total is distributed between the overrange and underrange capability. for example, if the underrange capability is 8lsb, the overrange capability is typically 31 C 8 = 23lsb. output data format the ltc2452 generates a 16-bit direct binary encoded result. it is provided as a 16-bit serial stream through the sdo output pin under the control of the sck input pin (see figure 4). letting v in = (v in + C v in C ), the output code is given as 32768?v in /v ref + 32768. the frst bit output by the ltc2452, d15, is the msb, which is 1 for v in + v in C and 0 for v in + < v in C . this bit is followed by successively less signifcant bits (d14, d13...) until the lsb is output by the ltc2452. table 1 shows some example output codes. table 1. ltc2452 output data format differential input voltage v in + C v in C d15 (msb) d14 d13 d12...d2 d1 d0 (lsb) corresponding decimal value v ref 1 1 1 1 1 1 65535 v ref C 1lsb 1 1 1 1 1 0 65534 0.5 ? v ref 1 1 0 0 0 0 49152 0.5 ? v ref C 1lsb 1 0 1 1 1 1 49151 0 1 0 0 0 0 0 32768 C1lsb 0 1 1 1 1 1 32767 C0.5 ? v ref 0 1 0 0 0 0 16384 C0.5 ? v ref C 1lsb 0 0 1 1 1 1 16383 Cv ref 0 0 0 0 0 0 0 v in + /v ref + ?0.001 output code 4 12 20 0.001 2452 f03 ?4 ?12 0 8 16 ?8 ?16 ?20 ?0.005 0 0.005 0.0015 signals below gnd
ltc2452 9 2452fc applications information figure 4. data output timing d 15 lsb sdo sck d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 0 d 1 2452 f04 t 1 t 3 t kq t lsck t hsck t 2 cs msb during the data output operation the cs input pin must be pulled low ( cs = low). the data output process starts with the most signifcant bit of the result being present at the sdo output pin (sdo = d15) once cs goes low. a new data bit appears at the sdo output pin after each falling edge detected at the sck input pin. the output data can be reliably latched by the user using the rising edge of sck. conversion status monitor for certain applications, the user may wish to monitor the ltc2452 conversion status. this can be achieved by holding sck high during the conversion cycle. in this condition, whenever the cs input pin is pulled low (cs = low), the sdo output pin will provide an indication of the conversion status. sdo = high is an indication of a conversion cycle in progress while sdo = low is an indication of a completed conversion cycle. an example of such a sequence is shown in figure 5. conversion status monitoring, while possible, is not re - quired for ltc2452 as its conversion time is fxed and equal at approximately 16.6ms (23ms maximum). therefore, external timing can be used to determine the completion of a conversion cycle. serial interface the ltc2452 transmits the conversion result and receives the start of conversion command through a synchronous 3-wire interface. this interface can be used during the convert and sleep states to assess the conversion status and during the data output state to read the conversion result, and to trigger a new conversion. figure 5. conversion status monitoring mode sleep t 1 t 2 sdo sck = high convert 2452 f05 cs
ltc2452 10 2452fc applications information serial interface operation modes the modes of operation can be summarized as follows: 1) the ltc2452 functions with sck idle high (commonly known as cpol = 1) or idle low (commonly known as cpol = 0). 2) after the 16th bit is read, the user can choose one of two ways to begin a new conversion. first, one can pull cs high (cs = ). second, one can use a high-low transition on sck (sck = ). 3) at any time during the data output state, pulling cs high (cs = ) causes the part to leave the i/o state, abort the output and begin a new conversion. 4) when sck = high, it is possible to monitor the conver - sion status by pulling cs low and watching for sdo to go low. this feature is available only in the idle-high (cpol = 1) mode. serial clock idle-high (cpol = 1) examples in figure 6, following a conversion cycle the ltc2452 automatically enters the low power sleep mode. the user can monitor the conversion status at convenient intervals using cs and sdo. pulling cs low while sck is high tests whether or not the chip is in the convert state. while in the convert state, sdo is high while cs is low. in the sleep state, sdo is low while cs is low. these tests are not required operational steps but may be useful for some applications. when the data is available, the user applies 16 clock cycles to transfer the result. the cs rising edge is then used to initiate a new conversion. the operation example of figure 7 is identical to that of figure 6, except the new conversion cycle is triggered by the falling edge of the serial clock (sck). a 17th clock pulse is used to trigger a new conversion cycle. figure 6. idle-high (cpol = 1) serial clock operation example. the rising edge of cs starts a new conversion figure 7. idle-high (cpol = 1) clock operation example. a 17th clock pulse is used to trigger a new conversion cycle d 15 clk 1 clk 2 clk 3 clk 4 clk 15 clk 16 d 14 d 13 d 12 d 2 d 1 d 0 sd0 sck convert convert sleep data output 2452 f06 cs d 15 d 14 d 13 d 12 d 2 d 1 d 0 sd0 clk 1 clk 2 clk 3 clk 4 clk 15 clk 16 clk 17 sck convert convert sleep data output 2452 f07 cs
ltc2452 11 2452fc applications information serial clock idle-low (cpol = 0) examples in figure 8, following a conversion cycle the ltc2452 automatically enters the low-power sleep state. the user determines data availability (and the end of conversion) based upon external timing. the user then pulls cs low (cs = ) and uses 16 clock cycles to transfer the result. following the 16th rising edge of the clock, cs is pulled high (cs = ), which triggers a new conversion. the timing diagram in figure 9 is identical to that of figure 8, except in this case a new conversion is triggered by sck. the 16th sck falling edge triggers a new conversion cycle and the cs signal is subsequently pulled high. examples of aborting cycle using cs for some applications, the user may wish to abort the i/o cycle and begin a new conversion. if the ltc2452 is in the data output state, a cs rising edge clears the remain- ing data bits from the output registers, aborts the output cycle and triggers a new conversion. figure 10 shows an example of aborting an i/o with idle-high (cpol = 1) and figure 11 shows an example of aborting an i/o with idle-low (cpol = 0). a new conversion cycle can be triggered using the cs signal without having to generate any serial clock pulses as shown in figure 12. if sck is maintained at a low logic level, after the end of a conversion cycle, a new conver - figure 9. idle-low (cpol = 0) clock. the 16th sck falling edge triggers a new conversion figure 8. idle-low (cpol = 0) clock. cs triggers a new conversion d 15 d 14 d 13 d 12 d 2 d 1 d 0 clk 1 clk 2 clk 3 clk 4 clk 14 clk 15 clk 16 sck sd0 convert convert sleep data output 2452 f08 cs d 15 d 14 d 13 d 12 d 2 d 1 d 0 sd0 clk 1 clk 2 clk 3 clk 4 clk 15 clk 14 clk 16 sck convert convert sleep data output 2452 f09 cs
ltc2452 12 2452fc applications information figure 11. idle-low (cpol = 0) clock and aborted i/o example figure 12. idle-low (cpol = 0) clock and minimum data output length example figure 10. idle-high (cpol = 1) clock and aborted i/o example d 15 d 14 d 13 clk 1 clk 2 clk 4 clk 3 convert convert sleep data output 2452 f10 sd0 sck cs d 15 d 14 d 13 sd0 clk 1 clk 2 clk 3 sck convert convert sleep data output 2452 f11 cs sck = low sd0 convert convert sleep data output 2452 f12 d 15 cs
ltc2452 13 2452fc sion operation can be triggered by pulling cs low and then high. when cs is pulled low ( cs = low), sdo will output the sign (d15) of the result of the just completed conversion. while a low logic level is maintained at sck pin and cs is subsequently pulled high (cs = high) the remaining 15 bits of the result (d14:d0) are discarded and a new conversion cycle starts. following the aborted i/o, additional clock pulses in the convert state are acceptable, but excessive signal tran - sitions on sck can potentially create noise on the adc during the conversion, and thus may negatively infuence the conversion accuracy. 2-wire operation the 2-wire operation modes, while reducing the number of required control signals, should be used only if the ltc2452 low power sleep capability is not required. in addition the option to abort serial data transfers is no longer available. hardwire cs to gnd for 2-wire operation. figure 13. 2-wire, idle-high (cpol = 1) serial clock, operation example figure 13 shows a 2-wire operation sequence which uses an idle-high (cpol = 1) serial clock signal. the conversion status can be monitored at the sdo output. following a conversion cycle, the adc enters sleep state and the sdo output transitions from high to low. subsequently 16 clock pulses are applied to the sck input in order to serially shift the 16 bit result. finally, the 17th clock pulse is applied to the sck input in order to trigger a new conversion cycle. figure 14 shows a 2-wire operation sequence which uses an idle-low (cpol = 0) serial clock signal. the conversion status cannot be monitored at the sdo output. following a conversion cycle, the ltc2452 bypasses the sleep state and immediately enters the data output state. at this moment the sdo pin outputs the sign (d15) of the conversion result. the user must use external timing in order to determine the end of conversion and result avail - ability. subsequently 16 clock pulses are applied to sck in order to serially shift the 16-bit result. the 16th clock falling edge triggers a new conversion cycle. applications information figure 14. 2-wire, idle-low (cpol = 0) serial clock operation example 2452 f13 d 15 d 14 d 13 d 12 d 2 d 1 d 0 sd0 clk 1 clk 2 clk 3 clk 4 clk 15 clk 16 clk 17 sck convert convert sleep data output cs = low 2452 f14 d 15 d 14 d 13 d 12 d 2 d 1 d 0 sd0 cs = low clk 1 clk 2 clk 3 clk 14 clk 4 clk 15 clk 16 sck convert convert data output
ltc2452 14 2452fc applications information preserving the converter accuracy the ltc2452 is designed to minimize the conversion results sensitivity to device decoupling, pcb layout, antialiasing circuits, line and frequency perturbations. nevertheless, in order to preserve the high accuracy capability of this part, some simple precautions are desirable. digital signal levels due to the nature of cmos logic, it is advisable to keep input digital signals near gnd or v cc . voltages in the range of 0.5v to v cc C 0.5v may result in additional current leakage from the part. undershoot and overshoot should also be minimized, particularly while the chip is converting. it is thus benefcial to keep edge rates of about 10ns and limit overshoot and undershoot to less than 0.3v. noisy external circuitry can potentially impact the output under 2-wire operation. in particular, it is possible to get the ltc2452 into an unknown state if an sck pulse is missed or noise triggers an extra sck pulse. in this situ - ation, it is impossible to distinguish sdo = 1 (indicating conversion in progress) from valid 1 data bits. as such, cpol = 1 is recommended for the 2-wire mode. the user should look for sdo = 0 before reading data, and look for sdo = 1 after reading data. if sdo does not return a 0 within the maximum conversion time (or return a 1 after a full data read), generate 16 sck pulses to force a new conversion. driving v cc and gnd in relation to the v cc and gnd pins, the ltc2452 combines internal high frequency decoupling with damping elements, which reduce the adc performance sensitivity to pcb layout and external components. nevertheless, the very high accuracy of this converter is best preserved by careful low and high frequency power supply decoupling. a 0.1f, high quality, ceramic capacitor in parallel with a 10f ceramic capacitor should be connected between the v cc and gnd pins, as close as possible to the package. the 0.1f capacitor should be placed closest to the adc package. it is also desirable to avoid any via in the circuit path, starting from the converter v cc pin, passing through these two decoupling capacitors, and returning to the converter gnd pin. the area encompassed by this circuit path, as well as the path length, should be minimized. furthermore, as shown in figure 15, gnd is used as the negative reference voltage. it is thus important to keep the gnd line quiet and connect gnd through a low-imped - ance trace. very low impedance ground and power planes, and star connections at both v cc and gnd pins, are preferable. the v cc pin should have two distinct connections: the frst to the decoupling capacitors described above, and the second to the ground return for the power supply voltage source. driving ref a simplifed equivalent circuit for ref is shown in figure 15. like all other a/d converters, the ltc2452 is only as accurate as the reference it is using. therefore, it is important to keep the reference line quiet by careful low and high frequency decoupling. figure 15. ltc2452 analog input/reference equivalent circuit r sw 15k (typ) i leak i leak v cc v cc v cc v cc c eq 0.35pf (typ) in + in ? gnd ref 2452 f15 r sw 15k (typ) i leak i leak r sw 15k (typ) i leak i leak r sw 15k (typ) i leak i leak
ltc2452 15 2452fc applications information the lt6660 reference is an ideal match for driving the ltc2452s ref pin. the ltc6660 is available in a 2mm 2mm dfn package with 2.5v, 3v, 3.3v and 5v options. a 0.1f, high quality, ceramic capacitor in parallel with a 10f ceramic capacitor should be connected between the ref and gnd pins, as close as possible to the package. the 0.1f capacitor should be placed closest to the adc. driving v in + and v in C the input drive requirements can best be analyzed using the equivalent circuit of figure 16. the input signal v sig is connected to the adc input pins (in + and in C ) through an equivalent source resistance r s . this resistor includes both the actual generator source resistance and any additional optional resistors connected to the input pins. optional input capacitors c in are also connected to the adc input pins. this capacitor is placed in parallel with the adc input parasitic capacitance c par . depending on the pcb layout, c par has typical values between 2pf and 15pf. in addition, the equivalent circuit of figure 16 includes the converter equivalent internal resistor r sw and sampling capacitor c eq . figure 16. ltc2452 input drive equivalent circuit there are some immediate trade-offs in r s and c in without needing a full circuit analysis. increasing r s and c in can give the following benefts: 1) due to the ltc2452s input sampling algorithm, the input current drawn by either v in + or v in C over a conversion cycle is typically 50na. a high r s ? c in attenuates the high frequency components of the input current, and r s values up to 1k result in <1lsb error. 2) the bandwidth from v sig is reduced at the input pins (in + , in C ). this bandwidth reduction isolates the adc from high frequency signals, and as such provides simple antialiasing and input noise reduction. 3) switching transients generated by the adc are attenu - ated before they go back to the signal source. 4) a large c in gives a better ac ground at the input pins, helping reduce refections back to the signal source. 5) increasing r s protects the adc by limiting the current during an outside-the-rails fault condition. there is a limit to how large r s ? c in should be for a given application. increasing r s beyond a given point increases the voltage drop across r s due to the input current, to the point that signifcant measurement errors exist. additionally, for some applications, increasing the r s ? c in product too much may unacceptably attenuate the signal at frequencies of interest. for most applications, it is desirable to implement c in as a high-quality 0.1f ceramic capacitor and r s 1k. this capacitor should be located as close as possible to the actual v in package pin. furthermore, the area encompassed by this circuit path, as well as the path length, should be minimized. in the case of a 2-wire sensor that is not remotely grounded, it is desirable to split r s and place series resistors in the adc input line as well as in the sensor ground return line, which should be tied to the adc gnd pin using a star connection topology. i leak i leak r sw 15k (typ) i conv c in in + v cc sig + sig ? r s c eq 0.35pf (typ) c par + ? 2452 f16 i leak i leak r sw 15k (typ) i conv c in in ? v cc r s c eq 0.35pf (typ) c par + ?
ltc2452 16 2452fc applications information figure 17 shows the measured ltc2452 inl vs input voltage as a function of r s value with an input capacitor c in = 0.1f. in some cases, r s can be increased above these guidelines. the input current is zero when the adc is either in sleep or i/o modes. thus, if the time constant of the input rc circuit t = r s ? c in , is of the same order of magnitude or longer than the time periods between actual conversions, then one can consider the input current to be reduced correspondingly. these considerations need to be balanced out by the input signal bandwidth. the 3db bandwidth 1/(2pr s c in ). finally, if the recommended choice for c in is unacceptable for the users specifc application, an alternate strategy is to eliminate c in and minimize c par and r s . in practical terms, this confguration corresponds to a low impedance sensor directly connected to the adc through minimum length traces. actual applications include current measurements through low value sense resistors, temperature measure - ments, low impedance voltage source monitoring, and so on. the resultant inl vs v in is shown in figure 18. the measurements of figure 18 include a capacitor c par cor - responding to a minimum sized layout pad and a minimum width input trace of about 1 inch length. figure 17. measured inl vs input voltage, c in = 0.1f, v cc = 5v, t a = 25c figure 18. measured inl vs input voltage, c in = 0, v cc = 5v, t a = 25c differential input voltage (v) ?5 inl (lsb) 2 6 10 3 2452 f17 ?2 ?6 0 4 8 ?4 ?8 ?10 ?3?4 ?1?2 1 2 4 0 5 r s = 10k r s = 2k r s = 1k r s = 0 c in = 0.1f v cc = 5v t a = 25c differential input voltage (v) ?5 inl (lsb) 2 6 10 3 2452 f18 ?2 ?6 0 4 8 ?4 ?8 ?10 ?3?4 ?1?2 1 2 4 0 5 r s = 10k r s = 1k, 2k r s = 0 c in = 0 v cc = 5v t a = 25c
ltc2452 17 2452fc applications information signal bandwidth, transition noise and noise equivalent input bandwidth the ltc2452 includes a sinc 1 type digital flter with the frst notch located at f 0 = 60hz. as such, the 3db input signal bandwidth is 26.54hz. the calculated ltc2452 input signal attenuation vs frequency over a wide frequency range is shown in figure 19. the calculated ltc2452 input signal attenuation vs frequency at low frequencies is shown in figure 20. the converter noise level is about 2.2v rms and can be modeled by a white noise source connected at the input of a noise-free converter. on a related note, the ltc2452 uses two separate a/d converters to digitize the positive and negative inputs. each of these a/d converters has 2.2v rms transition noise. if one of the input voltages is within this small transition noise band, then the output will fuctuate one bit, regardless of the value of the other input voltage. if both of the input voltages are within their transition noise bands, the output can fuctuate 2 bits. for a simple system noise analysis, the v in drive circuit can be modeled as a single-pole equivalent circuit character - ized by a pole location f i and a noise spectral density n i . if the converter has an unlimited bandwidth, or at least a bandwidth substantially larger than f i , then the total noise contribution of the external drive circuit would be: v n = n i p / 2 ? f i then, the total system noise level can be estimated as the square root of the sum of (v n 2 ) and the square of the ltc2452 noise foor (~2.2v 2 ). figure 19. ltc2452 input signal attentuation vs frequency figure 20. ltc2452 input signal attenuation vs frequency (low frequencies) input signal frequency (mhz) 0 input signal attenuation (db) ?40 0 1.00 1.25 1.50 2452 f19 ?60 ?80 ?20 ?100 2.5 5.0 7.5 input signal frequency (hz) 0 input signal attenuatioin (db) ?20 ?10 0 480 2452 f20 ?30 ?40 ?25 ?15 ?5 ?35 ?45 ?50 12060 240180 360 420 540 300 600
ltc2452 18 2452fc typical application 0.1f v cc in + in ? 2452 ta02 0.1f 92 43 0.1f 0.1f 0.1f 1k 1k 42 gndgnd 1f 1f 1k in out u2 lt6660hcdc-5 v + 3 1 5 6 8 1 7 v cc v cc gnd ref + 10v 5v cs sck/scl mosi/sda miso/sdo gnd gnd gnd 1 2 6 4 7 5 1f v cc v + 1383 to controller cs sck sdo 1 2 3 ext +5v jp1 u1* in + ref + ref ? v cc gnd in ? ltc2452 cs sck sdo
ltc2452 19 2452fc package description ddb package 8-lead plastic dfn (3mm 2mm) (reference ltc dwg # 05-08-1702 rev b) 2.00 0.10 (2 sides) note: 1. drawing conforms to version (wecd-1) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 0.56 0.05 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.05 typ 2.15 0.05 (2 sides) 3.00 0.10 (2 sides) 1 4 8 5 pin 1 bar top mark (see note 6) 0.200 ref 0 ? 0.05 (ddb8) dfn 0905 rev b 0.25 0.05 0.50 bsc pin 1 r = 0.20 or 0.25 45 chamfer 0.25 0.05 2.20 0.05 (2 sides) recommended solder pad pitch and dimensions 0.61 0.05 (2 sides) 1.15 0.05 0.70 0.05 2.55 0.05 package outline 0.50 bsc
ltc2452 20 2452fc package description ts8 package 8-lead plastic tsot-23 (reference ltc dwg # 05-08-1637 rev a) 1.50 ? 1.75 (note 4) 2.80 bsc 0.22 ? 0.36 8 plcs (note 3) datum ?a? 0.09 ? 0.20 (note 3) ts8 tsot-23 0710 rev a 2.90 bsc (note 4) 0.65 bsc 1.95 bsc 0.80 ? 0.90 1.00 max 0.01 ? 0.10 0.20 bsc 0.30 ? 0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.40 max 0.65 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref
ltc2452 21 2452fc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number c 03/10 updated analog inputs and references section added text to input voltage range section 3 8 (revision history begins at rev c)
ltc2452 22 2452fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax : (408) 434-0507 l www.linear.com linear technology corporation 2008 lt 0311 rev c ? printed in usa related parts part number description comments LT1236A-5 precision bandgap reference, 5v 0.05% max, 5ppm/c drift lt1461 micropower series reference, 2.5v 0.04% max, 3ppm/c drift lt1790 micropower precision reference in tsot-23-6 package 60a max supply current, 10ppm/c max drift, 1.25v, 2.048v, 2.5v, 3v, 3.3v, 4.096v and 5v options ltc1860/ltc1861 12-bit, 5v, 1-/2-channel 250ksps sar adc in msop 850a at 250ksps, 2a at 1ksps, so-8 and msop packages ltc1860l/ltc1861l 12-bit, 3v, 1-/2-channel 150ksps sar adc 450a at 150ksps, 10a at 1ksps, so-8 and msop packages ltc1864/ltc1865 16-bit, 5v, 1-/2-channel 250ksps sar adc in msop 850a at 250ksps, 2a at 1ksps, so-8 and msop packages ltc1864l/ltc1865l 16-bit, 3v, 1-/2-channel 150ksps sar adc 450a at 150ksps, 10a at 1ksps, so-8 and msop packages ltc2440 24-bit no latency )8 ? adc 200nv rms noise, 4khz output rate, 15ppm inl ltc2480 16-bit, differential input, no latency )8 adc, with pga, temp. sensor, spi easy-drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc2481 16-bit, differential input, no latency )8 adc, with pga, temp. sensor, i 2 c easy-drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc2482 16-bit, differential input, no latency )8 adc, spi easy-drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc2483 16-bit, differential input, no latency )8 adc, i 2 c easy-drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc2484 24-bit, differential input, no latency )8 adc, spi with temp. sensor easy-drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc2485 24-bit, differential input, no latency )8 adc, i 2 c with temp. sensor easy-drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc6241 dual, 18mhz, low noise, rail-to-rail op amp 550nv p-p noise, 125v offset max lt6660 micropower references in 2mm 2mm dfn package, 2.5v, 3v, 3.3v, 5v 20ppm/c max drift, 0.2% max ltc2450 easy-to-use, ultra-tiny 16-bit adc, spi 2 lsb inl, 50na sleep current, tiny 2mm 2mm dfn-6 package, 30hz output rate ltc2450-1 easy-to-use, ultra-tiny 16-bit adc, spi 2 lsb inl, 50na sleep current, tiny 2mm 2mm dfn-6 package, 60hz output rate ltc2451 easy-to-use, ultra-tiny 16-bit adc, i 2 c 2 lsb inl, 50na sleep current, tiny 3mm 2mm dfn-8 or tsot package, programmable 30hz/60hz output rates ltc2453 easy-to-use, ultra-tiny 16-bit differential adc, i 2 c 2 lsb inl, 50na sleep current, tiny 3mm 2mm dfn-8 or tsot package

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